VHDL报错 VHDL type mismatch error at shift.vhd(8): std_logic type does not match s
VHDL报错std - logic type does not match integer literal CASE JNK IS WHEN "00" => NULL; WHEN "01" => Q<='0';--你定义的Q是std_logic类型,但你赋值的时候由于没加单引号,被认为是integer类型了,所以应加单引号,下一句也是 WHEN "10" => Q<